Sciweavers

1563 search results - page 104 / 313
» Flexible instruction processors
Sort
View
114
Voted
HIPEAC
2009
Springer
15 years 7 months ago
MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor
Abstract. Threads experiencing long-latency loads on a simultaneous multithreading (SMT) processor may clog shared processor resources without making forward progress, thereby star...
Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhou...
129
Voted
ICS
2009
Tsinghua U.
15 years 7 months ago
High-performance regular expression scanning on the Cell/B.E. processor
Matching regular expressions (regexps) is a very common workload. For example, tokenization, which consists of recognizing words or keywords in a character stream, appears in ever...
Daniele Paolo Scarpazza, Gregory F. Russell
ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
15 years 6 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
15 years 5 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick
125
Voted
HPCA
2007
IEEE
16 years 1 months ago
Improving Branch Prediction and Predicated Execution in Out-of-Order Processors
If-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-predict branches, transforming control dependencies into data dependencies. Althou...
Eduardo Quiñones, Joan-Manuel Parcerisa, An...