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88
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ISCAS
2008
IEEE
133views Hardware» more  ISCAS 2008»
15 years 7 months ago
A hybrid self-testing methodology of processor cores
—Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new ho...
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
SAMOS
2004
Springer
15 years 6 months ago
A Low-Power Multithreaded Processor for Baseband Communication Systems
Embedded digital signal processors for baseband communication systems have stringent design constraints including high computational bandwidth, low power consumption, and low inter...
Michael J. Schulte, C. John Glossner, Suman Mamidi...
EUROPAR
2008
Springer
15 years 2 months ago
Performance Implications of Cache Affinity on Multicore Processors
Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity i...
Vahid Kazempour, Alexandra Fedorova, Pouya Alagheb...
104
Voted
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
16 years 1 months ago
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions
In the automatic design of custom instruction set processors, there can be a very large set of potential custom instructions, from which a few instructions are required to be chos...
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
81
Voted
DATE
2008
IEEE
62views Hardware» more  DATE 2008»
15 years 7 months ago
Instruction Cache Energy Saving Through Compiler Way-Placement
Fetching instructions from a set-associative cache in an embedded processor can consume a large amount of energy due to the tag checks performed. Recent proposals to address this ...
Timothy M. Jones, Sandro Bartolini, Bruno De Bus, ...