1563 search results - page 108 / 313 » Flexible instruction processors |
ISCA
1997
IEEE
15 years 5 months ago
1997
IEEE
Superscalar processors currently have the potential to fetch multiple basic blocks per cycle by employing one of several recently proposed instruction fetch mechanisms. However, t...
93
Voted
CASES
2010
ACM
14 years 10 months ago
2010
ACM
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...
91
Voted
HPCA
2008
IEEE
16 years 1 months ago
2008
IEEE
Serializing instructions (SIs), such as writes to control registers, have many complex dependencies, and are difficult to execute out-of-order (OoO). To avoid unnecessary complexi...
98
Voted
PLDI
2000
ACM
15 years 5 months ago
2000
ACM
{ This paper presents a new approach to local instruction scheduling based on integer programming that produces optimal instruction schedules in a reasonable time, even for very la...
92
Voted
HIPC
2000
Springer
15 years 4 months ago
2000
Springer
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the ...