Sciweavers

1563 search results - page 110 / 313
» Flexible instruction processors
Sort
View
96
Voted
SPAA
2003
ACM
15 years 6 months ago
Quantifying instruction criticality for shared memory multiprocessors
Recent research on processor microarchitecture suggests using instruction criticality as a metric to guide hardware control policies. Fields et al. [3, 4] have proposed a directed...
Tong Li, Alvin R. Lebeck, Daniel J. Sorin
97
Voted
CHES
2009
Springer
200views Cryptology» more  CHES 2009»
16 years 1 months ago
Accelerating AES with Vector Permute Instructions
We demonstrate new techniques to speed up the Rijndael (AES) block cipher using vector permute instructions. Because these techniques avoid data- and key-dependent branches and mem...
Mike Hamburg
DATE
2008
IEEE
107views Hardware» more  DATE 2008»
15 years 7 months ago
Instruction Set Extension Exploration in Multiple-Issue Architecture
To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized ins...
I-Wei Wu, Zhi-Yuan Chen, Jean Jyh-Jiun Shann, Chun...
105
Voted
MICRO
2002
IEEE
128views Hardware» more  MICRO 2002»
15 years 5 months ago
Compiler-directed instruction cache leakage optimization
Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consum...
Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut...
73
Voted
ISCA
1998
IEEE
143views Hardware» more  ISCA 1998»
15 years 5 months ago
Lockup-Free Instruction Fetch/Prefetch Cache Organization
In the past decade. there has been much literature describing various cache organizatrons that exploit general programming idiosyncrasies to obtain maxrmum hit rate (the probabili...
David Kroft