1563 search results - page 111 / 313 » Flexible instruction processors |
114
Voted
PLDI
1995
ACM
15 years 4 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
MICRO
2000
IEEE
15 years 17 days ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
128
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VEE
2006
ACM
15 years 6 months ago
2006
ACM
We present Vector LLVA, a virtual instruction set architecture (VISA) that exposes extensive static information about vector parallelism while avoiding the use of hardware-speci...
101
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DATE
2005
IEEE
15 years 6 months ago
2005
IEEE
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
103
Voted
IEEEPACT
2000
IEEE
15 years 5 months ago
2000
IEEE
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...