1563 search results - page 116 / 313 » Flexible instruction processors |
144
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SIGMETRICS
1996
ACM
15 years 5 months ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
107
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IPPS
2000
IEEE
15 years 5 months ago
2000
IEEE
The newly introduced Microprocessor Architecture for Java Computing MAJC supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruct...
84
Voted
EUROMICRO
1999
IEEE
15 years 5 months ago
1999
IEEE
This paper describes the DELFT-JAVA processor and the mechanisms required to dynamically translate JVM instructions into DELFT-JAVA instructions. Using a form of hardware register...
94
Voted
SIGCOMM
1996
ACM
15 years 5 months ago
1996
ACM
This paper describes several techniques designed to improve protocol latency, and reports on their effectiveness when measured on a modern RISC machine employing the DEC Alpha pro...
86
Voted
MICRO
2008
IEEE
15 years 7 months ago
2008
IEEE
Higher level of resource integration and the addition of new features in modern multi-processors put a significant pressure on their verification. Although a large amount of res...