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ASPLOS
2008
ACM
15 years 2 months ago
Communication optimizations for global multi-threaded instruction scheduling
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
Guilherme Ottoni, David I. August
101
Voted
SASP
2008
IEEE
164views Hardware» more  SASP 2008»
15 years 7 months ago
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications
This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The proces...
Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishito...
106
Voted
DAGSTUHL
2004
15 years 2 months ago
Requirements for and Design of a Processor with Predictable Timing
Abstract. This paper introduces a set of design principles that aim to make processor architectures amenable to static timing analysis. Based on these principles, we give a design ...
Christoph Berg, Jakob Engblom, Reinhard Wilhelm
FSE
2009
Springer
159views Cryptology» more  FSE 2009»
15 years 7 months ago
Intel's New AES Instructions for Enhanced Performance and Security
The Advanced Encryption Standard (AES) is the Federal Information Processing Standard for symmetric encryption. It is widely believed to be secure and efficient, and is therefore b...
Shay Gueron
121
Voted
ICMCS
2006
IEEE
152views Multimedia» more  ICMCS 2006»
15 years 6 months ago
Muli-Issue Multi-Threaded Stream Processor
The MISP Processor is a programmable media processor which supports multi-issuing, multi-threading and stream processing techniques. MISP executes applications that have been mapp...
Somayeh Sardashti, Hamid Reza Ghasemi, Omid Fatemi