1563 search results - page 123 / 313 » Flexible instruction processors |
105
click to vote
ASPLOS
1989
ACM
15 years 5 months ago
1989
ACM
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
111
click to vote
HICSS
1995
IEEE
15 years 4 months ago
1995
IEEE
Abstract. We reexamine the limits of parallelism available in programs, using runtime reconstruction of program data-flow graphs. While limits of parallelism have been examined in...
ISCAS
2007
IEEE
15 years 7 months ago
2007
IEEE
—Various instruction and transaction based power estimation techniques for processor and on-chip buses have been proposed in the past. In this paper, we propose a heterogeneous p...
SBACPAD
2003
IEEE
15 years 6 months ago
2003
IEEE
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...
90
Voted
ITC
1998
IEEE
15 years 5 months ago
1998
IEEE
New methodologies based on functional testing and built-in self-test can narrow the gap between necessary solutions and existing techniques for processor validation and testing. W...