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132
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IPCCC
1999
IEEE
15 years 5 months ago
Accurately modeling speculative instruction fetching in trace-driven simulation
Performance evaluation of modern, highly speculative, out-of-order microprocessors and the corresponding production of detailed, valid, accurate results have become serious challe...
R. Bhargava, L. K. John, F. Matus
107
Voted
MICRO
2002
IEEE
173views Hardware» more  MICRO 2002»
15 years 6 months ago
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
Christoforos E. Kozyrakis, David A. Patterson
ARVLSI
1999
IEEE
112views VLSI» more  ARVLSI 1999»
15 years 5 months ago
Architectural Considerations for Application-Specific Counterflow Pipelines
Application-specific processor design is a promising approach for meeting the performance and cost goals of a system. Application-specific processors are especially promising for ...
Bruce R. Childers, Jack W. Davidson
79
Voted
ICCD
2008
IEEE
109views Hardware» more  ICCD 2008»
15 years 10 months ago
Suitable cache organizations for a novel biomedical implant processor
— This paper evaluates various instruction- and data-cache organizations in terms of performance, power, energy and area on a suitably selected biomedical benchmark suite. The be...
Christos Strydis
86
Voted
IEEEPACT
2000
IEEE
15 years 5 months ago
Exploring Sub-Block Value Reuse for Superscalar Processors
The performance potential of a value reuse mechanism depends on its reuse detection time, the number of reuse opportunities, and the amount of work saved by skipping each reuse un...
Jian Huang, David J. Lilja