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IFIP
2010
Springer
14 years 6 months ago
A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement
Abstract. In this article, we present a flexible simulation environment for embedded real-time software refinement by a mixed level cosimulation. For this, ne the native speed of a...
Markus Becker, Henning Zabel, Wolfgang Müller...
ANCS
2007
ACM
15 years 3 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
EUROSYS
2010
ACM
15 years 9 months ago
A Comprehensive Scheduler for Asymmetric Multicore Systems
Symmetric-ISA (instruction set architecture) asymmetricperformance multicore processors were shown to deliver higher performance per watt and area for codes with diverse architect...
Juan Carlos Saez, Manuel Prieto Matias, Alexandra ...
ICCD
2004
IEEE
100views Hardware» more  ICCD 2004»
15 years 8 months ago
A Minimal Dual-Core Speculative Multi-Threading Architecture
Speculative Multi-Threading (SpMT) can improve single-threaded application performance using the multiple thread contexts available in current processors. We propose a minimal SpM...
Srikanth T. Srinivasan, Haitham Akkary, Tom Holman...
VEE
2010
ACM
327views Virtualization» more  VEE 2010»
15 years 6 months ago
AASH: an asymmetry-aware scheduler for hypervisors
Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs...
Vahid Kazempour, Ali Kamali, Alexandra Fedorova