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HPCA
2005
IEEE
16 years 6 days ago
On the Limits of Leakage Power Reduction in Caches
If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption in high performance processors. Caches, due to the f...
Yan Meng, Timothy Sherwood, Ryan Kastner
ICFP
2007
ACM
15 years 11 months ago
Faster laziness using dynamic pointer tagging
In the light of evidence that Haskell programs compiled by GHC exhibit large numbers of mispredicted branches on modern processors, we re-examine the "tagless" aspect of...
Simon Marlow, Alexey Rodriguez Yakushev, Simon L. ...
ASAP
2009
IEEE
143views Hardware» more  ASAP 2009»
15 years 9 months ago
Scalar Processing Overhead on SIMD-Only Architectures
—The Cell processor consists of a general-purpose core and eight cores with a complete SIMD instruction set. Although originally designed for multimedia and gaming, it is current...
Arnaldo Azevedo Filho, Ben H. H. Juurlink
ICCD
2007
IEEE
151views Hardware» more  ICCD 2007»
15 years 8 months ago
Benchmarks and performance analysis of decimal floating-point applications
The IEEE P754 Draft Standard for Floating-point Arithmetic provides specifications for Decimal Floating-Point (DFP) formats and operations. Based on this standard, many developer...
Liang-Kai Wang, Charles Tsen, Michael J. Schulte, ...
ICCD
2005
IEEE
114views Hardware» more  ICCD 2005»
15 years 8 months ago
Memory Bank Predictors
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio...