1563 search results - page 261 / 313 » Flexible instruction processors |
ICCAD
2005
IEEE
15 years 8 months ago
2005
IEEE
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
102
click to vote
LCTRTS
2010
Springer
15 years 6 months ago
2010
Springer
In this paper, we present a novel system modeling language which targets primarily the development of source-level multiprocessor memory aware optimizations. In contrast to previo...
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
RTOS Simulation Henning Zabel, Wolfgang Mueller Universität Paderborn, C-LAB Fürstenallee 11, D-33102 Paderborn, Germany —Today, mobile and embedded real-time systems have to c...
IISWC
2009
IEEE
15 years 6 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
CGO
2008
IEEE
15 years 6 months ago
2008
IEEE
We propose a new instruction, branch-on-random, that is like a standard conditional branch, except rather than specifying the condition on which the branch should be taken, it spe...