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IEEEPACT
2005
IEEE
15 years 5 months ago
Compiler Directed Early Register Release
This paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies regi...
Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abe...
ISPASS
2005
IEEE
15 years 5 months ago
Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection
Simulation-based microarchitecture research is often hindered by the slow speed of simulators. In this work, we propose a novel statistical technique to identify highly representa...
Ram Srinivasan, Jeanine Cook, Shaun Cooper
CGO
2003
IEEE
15 years 5 months ago
Retargetable and Reconfigurable Software Dynamic Translation
Software dynamic translation (SDT) is a technology that permits the modification of an executing program’s instructions. In recent years, SDT has received increased attention, f...
Kevin Scott, Naveen Kumar, S. Velusamy, Bruce R. C...
DATE
2003
IEEE
92views Hardware» more  DATE 2003»
15 years 5 months ago
An Integrated Approach for Improving Cache Behavior
The widening gap between processor and memory speeds renders data locality optimization a very important issue in data-intensive embedded applications. Throughout the years hardwa...
Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhar...
ISLPED
2003
ACM
91views Hardware» more  ISLPED 2003»
15 years 5 months ago
Reducing reorder buffer complexity through selective operand caching
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad ...