Sciweavers

1563 search results - page 272 / 313
» Flexible instruction processors
Sort
View
ASPDAC
2005
ACM
102views Hardware» more  ASPDAC 2005»
15 years 1 months ago
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
Oliver Schliebusch, Anupam Chattopadhyay, David Ka...
DAC
2005
ACM
15 years 1 months ago
Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
Antonio Carlos Schneider Beck, Luigi Carro
ERSA
2004
106views Hardware» more  ERSA 2004»
15 years 1 months ago
QOS Aware HW/SW Partitioning on Run-time Reconfigurable Multimedia Platforms
Advanced multimedia applications (e.g. based on MPEG-4) will consist of multiple scalable multimedia objects. This scalability enables the application to adapt to different proces...
Nam Pham Ngoc, Gauthier Lafruit, Jean-Yves Mignole...
MASCOTS
1997
15 years 1 months ago
A Hybrid Simulation Approach Enabling Performance Characterization of Large Software Systems
We describe a method for performance analysis of large software systems that combines a fast instruction-set simulator with off-line detailed analysis of segments of the execution...
Bengt Werner, Peter S. Magnusson
CORR
2010
Springer
89views Education» more  CORR 2010»
14 years 12 months ago
Power optimized programmable embedded controller
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
M. Kamaraju, K. Lal Kishore, A. V. N. Tilak