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ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
15 years 4 months ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
15 years 4 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
EMSOFT
2006
Springer
15 years 3 months ago
Compiler-assisted leakage energy optimization for clustered VLIW architectures
Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. ...
Rahul Nagpal, Y. N. Srikant
CASES
2005
ACM
15 years 1 months ago
A post-compilation register reassignment technique for improving hamming distance code compression
Code compression is a field where compression ratios between compiler-generated code and subsequent compressed code are highly dependent on decisions made at compile time. Most op...
Montserrat Ros, Peter Sutton
CASCON
2004
127views Education» more  CASCON 2004»
15 years 1 months ago
A quantitative analysis of the performance impact of specialized bytecodes in java
Java is implemented by 201 bytecodes that serve the same purpose as assembler instructions while providing object-file platform independence. A collection of core bytecodes provid...
Ben Stephenson, Wade Holst