1563 search results - page 299 / 313 » Flexible instruction processors |
100
click to vote
ISCA
2006
IEEE
15 years 5 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
MICRO
2006
IEEE
15 years 5 months ago
2006
IEEE
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
106
Voted
RTSS
2006
IEEE
15 years 5 months ago
2006
IEEE
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
CGO
2005
IEEE
15 years 5 months ago
2005
IEEE
The growing complexity of modern processors has made the generation of highly efficient code increasingly difficult. Manual code generation is very time consuming, but it is oft...
IEEEPACT
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper presents a new technique for efficient usage of small trace caches. A trace cache can significantly increase the performance of wide out-oforder processors, but to be e...