1563 search results - page 304 / 313 » Flexible instruction processors |
HPDC
1997
IEEE
15 years 4 months ago
1997
IEEE
This paper presents a novel networking architecture designed for communication intensive parallel applications running on clusters of workstations (COWs) connected by highspeed ne...
107
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MICRO
1997
IEEE
15 years 4 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
109
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EUROPAR
1997
Springer
15 years 3 months ago
1997
Springer
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
NIXDORF
1992
15 years 3 months ago
1992
We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [2]. Based on Field Programmable Gate Array (...
SP
2010
IEEE
15 years 3 months ago
2010
IEEE
Abstract—Most security mechanisms proposed to date unquestioningly place trust in microprocessor hardware. This trust, however, is misplaced and dangerous because microprocessors...