1563 search results - page 30 / 313 » Flexible instruction processors |
87
Voted
DAC
1999
ACM
16 years 1 months ago
1999
ACM
It is generally believed that there will be little more variety in CPU architectures, and thus the design of Instruction-set Architectures (ISAs) will have no role in the future o...
110
click to vote
JUCS
2008
15 years 23 days ago
2008
: This paper1 presents an instruction scheduling algorithm based on the Subgraph Isomorphism Problem. Given a Directed Acyclic Graph (DAG) G1, our algorithm looks for a subgraph G2...
SAMOS
2004
Springer
15 years 6 months ago
2004
Springer
Today’s Application Specific Instruction-set Processor (ASIP) design methodology often employs centralized Architecture Description Language (ADL) processor models, from which s...
105
Voted
OTM
2004
Springer
15 years 6 months ago
2004
Springer
Cache memories are mandatory to bridge the growing gap between CPU speed and main memory access time. Standard cache organizations improve the average execution time but are diffi...
130
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EURODAC
1995
IEEE
15 years 4 months ago
1995
IEEE
This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this...