1563 search results - page 47 / 313 » Flexible instruction processors |
106
Voted
JSA
2008
15 years 21 days ago
2008
In this paper, we present linear processor array architectures for flexible approximate string matching. These architectures are based on parallel realization of dynamic programmi...
CF
2006
ACM
15 years 6 months ago
2006
ACM
There is a continuous research effort devoted to overcome the memory wall problem. Prefetching is one of the most frequently used techniques. A prefetch mechanism anticipates the ...
111
Voted
LCTRTS
2007
Springer
15 years 6 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
143
Voted
IEEEPACT
2002
IEEE
15 years 5 months ago
2002
IEEE
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
113
Voted
CF
2008
ACM
15 years 2 months ago
2008
ACM
The current methodology used in mass-market processor design is to create a single base microarchitecture (e.g., Intel's "Core"or AMD's"K8") that is ...