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113
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MICRO
2000
IEEE
88views Hardware» more  MICRO 2000»
15 years 15 days ago
Two-level hierarchical register file organization for VLIW processors
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
Javier Zalamea, Josep Llosa, Eduard Ayguadé...
CJ
2006
84views more  CJ 2006»
15 years 23 days ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
ISVLSI
2008
IEEE
149views VLSI» more  ISVLSI 2008»
15 years 7 months ago
Uncriticality-Directed Low-Power Instruction Scheduling
Intelligent mobile information devices require lowpower and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed ...
Shingo Watanabe, Toshinori Sato
162
Voted
ISCA
1998
IEEE
155views Hardware» more  ISCA 1998»
15 years 5 months ago
A Study of Branch Prediction Strategies
In high-performance computer systems, performance losses due to conditional branch instructions can be minimized by predicting a branch outcome and fetching, decoding, and/or issu...
James E. Smith
103
Voted
ERSA
2009
185views Hardware» more  ERSA 2009»
14 years 10 months ago
Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX
In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Uni...
Mariusz Grad, Christian Plessl