1563 search results - page 74 / 313 » Flexible instruction processors |
105
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MICRO
1995
IEEE
15 years 4 months ago
1995
IEEE
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
110
Voted
PAIRING
2007
Springer
15 years 6 months ago
2007
Springer
A series of recent algorithmic advances has delivered highly effective methods for pairing evaluation and parameter generation. However, the resulting multitude of options means m...
123
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DATE
2005
IEEE
15 years 6 months ago
2005
IEEE
Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compil...
91
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ASAP
2000
IEEE
15 years 5 months ago
2000
IEEE
MicroSIMD architectures incorporating subword parallelism are very efficient for application-specific media processors as well as for fast multimedia information processing in gen...
108
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CASES
2007
ACM
15 years 4 months ago
2007
ACM
Delayed branching is a technique to alleviate branch hazards without expensive hardware branch prediction mechanisms. For VLIW processors with deep pipelines and many issue slots,...