Sciweavers

1563 search results - page 75 / 313
» Flexible instruction processors
Sort
View
104
Voted
ASAP
2005
IEEE
93views Hardware» more  ASAP 2005»
15 years 2 months ago
Instruction Set Extensions for Reed-Solomon Encoding and Decoding
Reed-Solomon codes are an important class of error correcting codes used in many applications related to communications and digital storage. The fundamental operations in Reed-Sol...
Suman Mamidi, Daniel Iancu, Andrei Iancu, Michael ...
74
Voted
IPPS
2006
IEEE
15 years 6 months ago
Empowering a helper cluster through data-width aware instruction selection policies
Narrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- a...
Osman S. Unsal, Oguz Ergin, Xavier Vera, Antonio G...
101
Voted
ICPP
1993
IEEE
15 years 4 months ago
Meta-State Conversion
Abstract — In MIMD (Multiple Instruction stream, Multiple Data stream) execution, each processor has its own state. Although these states are generally considered to be independe...
Henry G. Dietz, G. Krishnamurthy
99
Voted
RTSS
2008
IEEE
15 years 7 months ago
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
With the advent of increasingly complex hardware in realtime embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), ...
Damien Hardy, Isabelle Puaut
112
Voted
ICS
1999
Tsinghua U.
15 years 5 months ago
Classifying load and store instructions for memory renaming
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary ...