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108
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ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
15 years 4 months ago
Generating instruction sets and microarchitectures from applications
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
Ing-Jer Huang, Alvin M. Despain
ASPLOS
2006
ACM
15 years 4 months ago
Instruction scheduling for a tiled dataflow architecture
This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effective...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
101
Voted
APCSAC
2006
IEEE
15 years 6 months ago
A Study of the Performance Potential for Dynamic Instruction Hints Selection
Abstract. Instruction hints have become an important way to communicate compile-time information to the hardware. They can be generated by the compiler and the post-link optimizer ...
Rao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu
97
Voted
CF
2008
ACM
15 years 2 months ago
Low power microarchitecture with instruction reuse
Power consumption has become a very important metric and challenging research topic in the design of microprocessors in the recent years. The goal of this work is to improve power...
Frederico Pratas, Georgi Gaydadjiev, Mladen Bereko...
ICCD
2004
IEEE
101views Hardware» more  ICCD 2004»
15 years 9 months ago
Increasing Processor Performance Through Early Register Release
Modern superscalar microprocessors need sizable register files to support large number of in-flight instructions for exploiting ILP. An alternative to building large register file...
Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kan...