1563 search results - page 82 / 313 » Flexible instruction processors |
82
Voted
ISCA
2000
IEEE
15 years 5 months ago
2000
IEEE
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor ...
86
Voted
DAC
2002
ACM
16 years 1 months ago
2002
ACM
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most ...
105
Voted
IPPS
2003
IEEE
15 years 6 months ago
2003
IEEE
Fine-grained parallel applications require all their processes to run simultaneously on distinct processors to achieve good efficiency. This is typically accomplished by space sl...
83
Voted
ISCA
1999
IEEE
15 years 5 months ago
1999
IEEE
Value Prediction is a relatively new technique to increase instruction-level parallelism by breaking true data dependence chains. A value prediction architecture produces values, ...
HIPEAC
2009
Springer
15 years 4 months ago
2009
Springer
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...