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MICRO
1994
IEEE
85views Hardware» more  MICRO 1994»
15 years 4 months ago
A high-performance microarchitecture with hardware-programmable functional units
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Rahul Razdan, Michael D. Smith
DSN
2004
IEEE
15 years 4 months ago
An Architectural Framework for Providing Reliability and Security Support
This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE)...
Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. ...
NIPS
1997
15 years 2 months ago
Learning to Schedule Straight-Line Code
Program execution speed on modern computers is sensitive, by a factor of two or more, to the order in which instructions are presented to the processor. To realize potential execu...
J. Eliot B. Moss, Paul E. Utgoff, John Cavazos, Do...
DATE
2008
IEEE
139views Hardware» more  DATE 2008»
15 years 7 months ago
Instruction Re-encoding Facilitating Dense Embedded Code
Reducing the code size of embedded applications is one of the important constraint in embedded system design. Code compression can provide substantial savings in terms of size. In...
Talal Bonny, Jörg Henkel
DATE
2007
IEEE
101views Hardware» more  DATE 2007»
15 years 7 months ago
Polynomial-time subgraph enumeration for automated instruction set extension
This paper proposes a novel algorithm that, given a data-flow graph and an input/output constraint, enumerates all convex subgraphs under the given constraint in polynomial time ...
Paolo Bonzini, Laura Pozzi