Sciweavers

1563 search results - page 88 / 313
» Flexible instruction processors
Sort
View
LCTRTS
2001
Springer
15 years 5 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
15 years 4 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
SAC
2008
ACM
15 years 6 days ago
Filtering drowsy instruction cache to achieve better efficiency
Leakage power in cache memories represents a sizable fraction of total power consumption, and many techniques have been proposed to reduce it. As a matter of fact, during a fixed ...
Roberto Giorgi, Paolo Bennati
95
Voted
HICSS
1994
IEEE
118views Biometrics» more  HICSS 1994»
15 years 4 months ago
A Distributed Architecture for an Instructable Problem Solver
Our research goal is to design systems that enable humans to teach tedious, repetitive, simple tasks to a computer. We propose here a learner/problem solver architecture for such ...
Jacky Baltes, Bruce A. MacDonald
SBACPAD
2004
IEEE
86views Hardware» more  SBACPAD 2004»
15 years 2 months ago
Multi-Profile Instruction Based Compression
Code compression has been used to minimize the memory area requirement of embedded systems. Recently, performance improvement and energy consumption reductionare observed as a by-...
Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Ce...