1563 search results - page 89 / 313 » Flexible instruction processors |
144
Voted
ISCA
2008
IEEE
15 years 7 months ago
2008
IEEE
Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunc...
117
Voted
ICESS
2007
Springer
15 years 6 months ago
2007
Springer
Compact code generation is very important for an embedded system that has to be implemented on a chip with a severely limited amount of size. Even though on-chip data memory optimi...
IPPS
2005
IEEE
15 years 6 months ago
2005
IEEE
We study the energy efficiency benefits of bypassing trivial computations in high-performance processors. Trivial computations are those computations whose output can be determine...
113
Voted
ISCA
2003
IEEE
15 years 6 months ago
2003
IEEE
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
115
click to vote
CODES
2007
IEEE
15 years 7 months ago
2007
IEEE
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...