1563 search results - page 92 / 313 » Flexible instruction processors |
135
Voted
IEEEPACT
2008
IEEE
15 years 7 months ago
2008
IEEE
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
99
Voted
MICRO
2010
IEEE
14 years 10 months ago
2010
IEEE
Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scien...
94
Voted
PPL
2008
15 years 20 days ago
2008
This discussion paper explores the problems of operating systems support when implementing concurrency controls at the level of the instruction set in processors designed for mult...
107
click to vote
WSC
1997
15 years 2 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
148
click to vote
ECRTS
2006
IEEE
15 years 6 months ago
2006
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...