1563 search results - page 97 / 313 » Flexible instruction processors |
159
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VLSID
1999
IEEE
15 years 5 months ago
1999
IEEE
In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific...
94
Voted
ASYNC
1998
IEEE
15 years 5 months ago
1998
IEEE
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs a...
95
Voted
HPCA
2007
IEEE
16 years 1 months ago
2007
IEEE
A thread executing on a simultaneous multithreading (SMT) processor that experiences a long-latency load will eventually stall while holding execution resources. Existing long-lat...
110
Voted
CODES
2006
IEEE
15 years 6 months ago
2006
IEEE
Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed software-only approaches suffe...
112
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CF
2004
ACM
15 years 6 months ago
2004
ACM
Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The conse...