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113
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CGO
2006
IEEE
15 years 6 months ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal
98
Voted
HPCA
1999
IEEE
15 years 5 months ago
A Study of Control Independence in Superscalar Processors
Control independence has been put forward as a significant new source of instruction-level parallelism for future generation processors. However, its performance potential under p...
Eric Rotenberg, Quinn Jacobson, James E. Smith
109
Voted
MICRO
1997
IEEE
79views Hardware» more  MICRO 1997»
15 years 5 months ago
On High-Bandwidth Data Cache Design for Multi-Issue Processors
Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The nu...
Jude A. Rivers, Gary S. Tyson, Edward S. Davidson,...
MICRO
1993
IEEE
127views Hardware» more  MICRO 1993»
15 years 4 months ago
An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors
The conventional classification of inter-instruction dependencies (data, anti and output dependencies) provides a basic scheme for the analysis of pipeline hazards in pipelined in...
Ing-Jer Huang, Alvin M. Despain
SODA
2001
ACM
125views Algorithms» more  SODA 2001»
15 years 2 months ago
Parallel processor scheduling with delay constraints
We consider the problem of scheduling unit-length jobs on identical parallel machines such that the makespan of the resulting schedule is minimized. Precedence constraints impose ...
Daniel W. Engels, Jon Feldman, David R. Karger, Ma...