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» Floorplanning for Partial Reconfiguration in FPGAs
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VLSID
2005
IEEE
128views VLSI» more  VLSID 2005»
15 years 11 months ago
On-Line Synthesis for Partially Reconfigurable FPGAs
An important application of dynamically and partially reconfigurable computing platforms is in dynamic task allocation and execution. On-line synthesis, on-line placement and on-l...
Renqiu Huang, Ranga Vemuri
ERSA
2010
186views Hardware» more  ERSA 2010»
14 years 9 months ago
DAPR: Design Automation for Partially Reconfigurable FPGAs
Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...
Shaon Yousuf, Ann Gordon-Ross
ARC
2007
Springer
120views Hardware» more  ARC 2007»
15 years 3 months ago
Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs
Abstract. Conventional rigid router-based networks on chip incur certain overheads due to huge occupied logic resources and topology embedding, i.e., the mapping of a logical netwo...
Jae Young Hur, Stephan Wong, Stamatis Vassiliadis
DATE
2003
IEEE
98views Hardware» more  DATE 2003»
15 years 4 months ago
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs
Fernando Gehm Moraes, Daniel Mesquita, José...