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» Floorplanning with Datapath Optimization
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ICCAD
1995
IEEE
78views Hardware» more  ICCAD 1995»
15 years 1 months ago
A unified approach to topology generation and area optimization of general floorplans
Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab...
TODAES
2008
50views more  TODAES 2008»
14 years 9 months ago
Optimizing wirelength and routability by searching alternative packings in floorplanning
Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou
HIPEAC
2007
Springer
15 years 1 months ago
Customizing the Datapath and ISA of Soft VLIW Processors
In this paper, we examine the trade-offs in performance and area due to customizing the datapath and instruction set architecture of a soft VLIW processor implemented in a high-den...
Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Ak...
74
Voted
ASPDAC
2007
ACM
81views Hardware» more  ASPDAC 2007»
15 years 1 months ago
LEAF: A System Level Leakage-Aware Floorplanner for SoCs
Abstract-- Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage ...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
DAC
2002
ACM
15 years 10 months ago
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans
We extend in this paper the concept of the P-admissible floorplan representation to that of the P*-admissible one. A P*-admissible representation can model the most general floorp...
Jai-Ming Lin, Yao-Wen Chang