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» Floorplanning with Datapath Optimization
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VLSID
2009
IEEE
142views VLSI» more  VLSID 2009»
15 years 10 months ago
Floorplanning for Partial Reconfiguration in FPGAs
Partial Reconfiguration on heterogeneous Field Programmable Gate Arrays (FPGA) with millions of gates yields better utilization of resources by swapping in and out the active modu...
Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay
ISPD
1999
ACM
97views Hardware» more  ISPD 1999»
15 years 1 months ago
A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, ...
ASPDAC
2004
ACM
101views Hardware» more  ASPDAC 2004»
15 years 3 months ago
A sub-mW MPEG-4 motion estimation processor core for mobile video application
This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It features a Gradient Descent Search algorithm whose computation power is only 7% of the...
Yuki Kuroda, Junichi Miyakoshi, Masayuki Miyama, K...
ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
15 years 3 months ago
Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
Saraju P. Mohanty, Elias Kougianos, Ramakrishna Ve...
ICCAD
2007
IEEE
124views Hardware» more  ICCAD 2007»
15 years 6 months ago
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits
Abstract— Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized du...
Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. ...