161 search results - page 19 / 33 » Floorplanning with Datapath Optimization |
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
ISQED
2009
IEEE
15 years 4 months ago
2009
IEEE
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
— In this paper, we introduce a novel substrate noise estimation technique during early floorplanning, based on the concept of Block Preference Directed Graph (BPDG) and the cla...
ISPD
2005
ACM
15 years 3 months ago
2005
ACM
Research in floorplanning and block-packing has generated a variety of data structures to represent spatial configurations of circuit modules. Much of this work focuses on the g...
VLSID
2002
IEEE
15 years 2 months ago
2002
IEEE
Power supply noise is a strong function of the switching activities of the circuit modules. Peak power supply noise can be significantly reduced by judiciously arranging the modu...