161 search results - page 4 / 33 » Floorplanning with Datapath Optimization |
79
Voted
ARITH
2009
IEEE
15 years 4 months ago
2009
IEEE
Datapath synthesis for standard-cell design goes through extraction of arithmetic operations from RTL code, high-level arithmetic optimizations and netlist generation. Numerous ar...
75
Voted
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
As the size and complexity of VLSI circuits increase, the need for faster floorplanning algorithms also grows. In this work we introduce Traffic, a new method for creating wire- a...
ISPD
2003
ACM
15 years 2 months ago
2003
ACM
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
ESTIMEDIA
2005
Springer
15 years 3 months ago
2005
Springer
Designing Application-Specific Instruction-set Processors (ASIPs) usually requires designing a custom datapath, and modifying instruction-set, instruction decoder, and compiler. A...
FPGA
1995
ACM
15 years 1 months ago
1995
ACM
A novel approach is presented for transforming a given scheduled and bound signal processing algorithm for a multiplexer based datapath to a BUS/RAM based FPGA datapath. A datapat...