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» Floorplanning with Datapath Optimization
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85
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DAC
2008
ACM
15 years 10 months ago
DeFer: deferred decision making enabled fixed-outline floorplanner
In this paper, we present DeFer -- a fast, high-quality and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a non-slicing floorplan by compacting a slicing fl...
Jackey Z. Yan, Chris Chu
FCCM
2004
IEEE
98views VLSI» more  FCCM 2004»
15 years 1 months ago
Automated Least-Significant Bit Datapath Optimization for FPGAs
In this paper we present a method for FPGA datapath precision optimization subject to user-defined area and error constraints. This work builds upon our previous research [1] which...
Mark L. Chang, Scott Hauck
95
Voted
ICCAD
2010
IEEE
140views Hardware» more  ICCAD 2010»
14 years 7 months ago
Polynomial datapath optimization using constraint solving and formal modelling
For a variety of signal processing applications polynomials are implemented in circuits. Recent work on polynomial datapath optimization achieved significant reductions of hardware...
Finn Haedicke, Bijan Alizadeh, Görschwin Fey,...
ISQED
2005
IEEE
106views Hardware» more  ISQED 2005»
15 years 3 months ago
Thermal-Aware Floorplanning Using Genetic Algorithms
In this work, we present a genetic algorithm based thermal-aware floorplanning framework that aims at reducing hot spots and distributing temperature evenly across a chip while op...
Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, C...
ICCTA
2007
IEEE
15 years 1 months ago
Register Sharing Verification During Data-Path Synthesis
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sa...