161 search results - page 6 / 33 » Floorplanning with Datapath Optimization |
ASPDAC
2001
ACM
15 years 1 months ago
2001
ACM
One of the most challenging issues in today's high-performance VLSI design is to ensure high-quality power supply to each individual circuit blocks. Reduced power supply volt...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the fina...
ISPD
1997
ACM
15 years 1 months ago
1997
ACM
The inherent distortion of the structural regularity of VLSI datapaths after logic optimization has until now precluded dense regular layouts of optimized datapaths despite their ...
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
ICES
2003
Springer
15 years 2 months ago
2003
Springer
This paper presents a methodology to design optimized electronic systems from high abstraction level descriptions. The methodology uses Genetic Programming in addition to high-leve...