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» Floorplanning with Datapath Optimization
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ASPDAC
2009
ACM
124views Hardware» more  ASPDAC 2009»
15 years 2 months ago
Thermal optimization in multi-granularity multi-core floorplanning
—Multi-core microarchitectures require a careful balance between many competing objectives to achieve the highest possible performance. Integrated Early Analysis is the considera...
Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Lo...
ISQED
2002
IEEE
126views Hardware» more  ISQED 2002»
15 years 2 months ago
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-...
ASPDAC
2004
ACM
85views Hardware» more  ASPDAC 2004»
15 years 3 months ago
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one...
Yi-Hui Cheng, Yao-Wen Chang
DATE
2010
IEEE
119views Hardware» more  DATE 2010»
15 years 2 months ago
Exploiting local logic structures to optimize multi-core SoC floorplanning
Abstract—We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) sys...
Cheng-Hong Li, Sampada Sonalkar, Luca P. Carloni
ASPDAC
2007
ACM
100views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...