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DAC
2009
ACM
16 years 22 days ago
Flip-chip routing with unified area-I/O pad assignments for package-board co-design
In this paper, we present a novel flip-chip routing algorithm for package-board co-design. Unlike the previous works that can consider only either free- or pre-assignment routing,...
Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang
AUIC
2006
IEEE
15 years 5 months ago
User interface layout with ordinal and linear constraints
User interfaces as well as documents use tabular layout mechanisms. The HTML table construct and the GridBag layout in Java are typical examples. There are, however, shortcomings ...
Christof Lutteroth, Gerald Weber
FCCM
2011
IEEE
241views VLSI» more  FCCM 2011»
14 years 3 months ago
Multilevel Granularity Parallelism Synthesis on FPGAs
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
Alexandros Papakonstantinou, Yun Liang, John A. St...
DAMON
2008
Springer
15 years 1 months ago
Avoiding version redundancy for high performance reads in temporal databases
A major performance bottleneck for database systems is the memory hierarchy. The performance of the memory hierarchy is directly related to how the content of disk pages maps to t...
Khaled Jouini, Geneviève Jomier
VDA
2010
247views Visualization» more  VDA 2010»
15 years 2 months ago
Flow Web: a graph based user interface for 3D flow field exploration
While there have been intensive efforts in developing better 3D flow visualization techniques, little attention has been paid to the design of better user interfaces and more effe...
Lijie Xu, Han-Wei Shen