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DATE
2008
IEEE
118views Hardware» more  DATE 2008»
15 years 1 months ago
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices
Advanced MOSFETs such as Strained Silicon (SS) devices have emerged as critical enablers to keep Moore's law on track for sub100nm technologies. Use of Strained Silicon devic...
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
CODES
2006
IEEE
15 years 5 months ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
15 years 3 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
JGAA
2002
81views more  JGAA 2002»
14 years 11 months ago
Graph Drawing in Motion
Enabling the user of a graph drawing system to preserve the mental map between two different layouts of a graph is a major problem. In this paper we present methods that smoothly ...
Carsten Friedrich, Peter Eades
DATE
2010
IEEE
135views Hardware» more  DATE 2010»
15 years 4 months ago
Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits
— To overcome issues originating from the CMOS technology, a large-scale reconfigurable data-path (LSRDP) processor based on single-flux quantum circuits is introduced. LSRDP is ...
Farhad Mehdipour, Hiroaki Honda, Hiroshi Kataoka, ...