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143
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ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
16 years 18 days ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
197
Voted
AGTIVE
2007
Springer
15 years 7 months ago
Verification and Synthesis of OCL Constraints Via Topology Analysis
On the basis of a case-study, we demonstrate the usefulness of topology invariants for model-driven systems development. Considering a graph grammar semantics for a relevant fragme...
Jörg Bauer, Werner Damm, Tobe Toben, Bernd We...
101
Voted
HASE
2007
IEEE
15 years 10 months ago
Pattern-Based Modeling and Analysis of Failsafe Fault-Tolerance in UML
In order to facilitate incremental modeling and analysis of fault-tolerant embedded systems, we introduce an object analysis pattern, called the detector pattern, that provides a ...
Ali Ebnenasir, Betty H. C. Cheng
150
Voted
RTAS
2008
IEEE
15 years 10 months ago
Schedulability Analysis of MSC-based System Models
Message Sequence Charts (MSCs) are widely used for describing interaction scenarios between the components of a distributed system. Consequently, worst-case response time estimati...
Lei Ju, Abhik Roychoudhury, Samarjit Chakraborty
115
Voted
ARC
2009
Springer
137views Hardware» more  ARC 2009»
15 years 10 months ago
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep
This paper argues the case for the use of analytical models in FPGA architecture layout exploration. We show that the problem when simplified, is amenable to formal optimization t...
Asma Kahoul, George A. Constantinides, Alastair M....