475 search results - page 17 / 95 » Formal Analysis of Processor Timing Models |
CODES
2008
IEEE
15 years 3 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
NCA
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper, fundamental conditions which bound the network processing unit (NPU) worst-case performance are established. In particular, these conditions formalize and integrate...
ANSS
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper presents a simulation performance improvement of the application of the Multicomponent Discrete Time System Specification (MultiDTSS) formalism to a fire spread. Multic...
IEEEPACT
2007
IEEE
15 years 3 months ago
2007
IEEE
The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable. Howe...
BIRTHDAY
2010
Springer
14 years 10 months ago
2010
Springer
Abstract. To support model-based development and analysis of embedded systems, the specification language VDM++ has been extended with asynchronous communication and improved timin...