475 search results - page 23 / 95 » Formal Analysis of Processor Timing Models |
ASYNC
2005
IEEE
15 years 3 months ago
2005
IEEE
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
80
Voted
ICECCS
1998
IEEE
15 years 1 months ago
1998
IEEE
The main focus of this paper is the problem of ensuring timeliness in safety critical systems. First, we introduce a method and its associated technique to model both real-time ta...
FORMATS
2010
Springer
14 years 7 months ago
2010
Springer
Abstract. Probabilistic timed automata are an extension of timed automata with discrete probability distributions. Simulation and bisimulation relations are widely-studied in the c...
ISORC
2005
IEEE
15 years 3 months ago
2005
IEEE
As complexity of real-time embedded software grows, it is desirable to use formal verification techniques to achieve a high level of assurance. We discuss application of model-ch...
94
Voted
FAC
2000
14 years 9 months ago
2000
In this paper we present a method of describing microprocessors at different levels of temporal and data abstraction. We consider microprogrammed, pipelined and superscalar proces...