475 search results - page 30 / 95 » Formal Analysis of Processor Timing Models |
103
click to vote
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
CMSB
2007
Springer
15 years 3 months ago
2007
Springer
For modeling and analyzing regulatory networks based on qualitative information and possibly additional temporal constraints, approaches using hybrid automata can be very helpful. ...
IPPS
2005
IEEE
15 years 3 months ago
2005
IEEE
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
JOT
2010
14 years 8 months ago
2010
Validation of non-functional and functional properties of these protocols during the early stages of design and development is important to reduce cost resulting from protocol ano...
111
click to vote
ETFA
2006
IEEE
15 years 3 months ago
2006
IEEE
Abstract— This article presents some results about schedulability analysis of tasks with offsets also known as transactions, in the particular case of monotonic transactions. The...