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» Formal Analysis of Processor Timing Models
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DATE
2007
IEEE
128views Hardware» more  DATE 2007»
15 years 9 months ago
Accounting for cache-related preemption delay in dynamic priority schedulability analysis
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...
Lei Ju, Samarjit Chakraborty, Abhik Roychoudhury
ICCCN
2007
IEEE
15 years 9 months ago
Signaling Transport Options in GMPLS Networks: In-band or Out-of-band
—Signaling protocols for GMPLS networks have been standardized and implemented in switch controllers. Most switch vendors allow for signaling messages to be carried over inband s...
Malathi Veeraraghavan, Tao Li
ENTCS
2006
168views more  ENTCS 2006»
15 years 3 months ago
Case Study: Model Transformations for Time-triggered Languages
In this study, we introduce a model transformation tool for a time-triggered language: Giotto. The tool uses graphs to represent the source code (Giotto) and the target (the sched...
Tivadar Szemethy
120
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CPE
2003
Springer
149views Hardware» more  CPE 2003»
15 years 8 months ago
Logical and Stochastic Modeling with SMART
We describe the main features of SmArT, a software package providing a seamless environment for the logic and probabilistic analysis of complex systems. SmArT can combine differen...
Gianfranco Ciardo, R. L. Jones III, Andrew S. Mine...
ICDM
2007
IEEE
158views Data Mining» more  ICDM 2007»
15 years 9 months ago
On Appropriate Assumptions to Mine Data Streams: Analysis and Practice
Recent years have witnessed an increasing number of studies in stream mining, which aim at building an accurate model for continuously arriving data. Somehow most existing work ma...
Jing Gao, Wei Fan, Jiawei Han