21 search results - page 2 / 5 » Formal Design of Arithmetic Circuits Based on Arithmetic Des... |
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
If real number calculations are implemented as circuits, only a limited preciseness can be obtained. Hence, formal verification can not be used to prove the equivalence between th...
ANSS
2005
IEEE
13 years 12 months ago
2005
IEEE
When performed on a classical computer, the simulation of quantum circuits is usually an exponential job. The methodology based on Hardware Description Languages is able to isolat...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
—In this paper we describe a practical methodology to formally verify highly optimized, industrial multipliers. We a multiplier description language which abstracts from low-leve...
VLSID
2002
IEEE
14 years 6 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
DAC
1998
ACM
14 years 7 months ago
1998
ACM
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...