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» Formal Design of Arithmetic Circuits Based on Arithmetic Des...
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TCAD
2008
114views more  TCAD 2008»
13 years 6 months ago
Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog
el Predicate Abstraction and Refinement Techniques for Verifying RTL Verilog Himanshu Jain, Daniel Kroening, Natasha Sharygina, and Edmund M. Clarke, Fellow, IEEE As a first step, ...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...
POPL
2010
ACM
14 years 3 months ago
From Program Verification to Program Synthesis
This paper describes a novel technique for the synthesis of imperative programs. Automated program synthesis has the potential to make programming and the design of systems easier...
Saurabh Srivastava, Sumit Gulwani, Jeffrey S. Fost...
DATE
2007
IEEE
112views Hardware» more  DATE 2007»
14 years 18 days ago
Tool-support for the analysis of hybrid systems and models
This paper introduces a method and tool-support for the automatic analysis and verification of hybrid and embedded control systems, whose continuous dynamics are often modelled u...
Andreas Bauer 0002, Markus Pister, Michael Tautsch...
TSMC
2010
13 years 29 days ago
Probabilistic Model-Based Diagnosis: An Electrical Power System Case Study
Abstract--We present in this paper a case study of the probabilistic approach to model-based diagnosis. Here, the diagnosed system is a real-world electrical power system (EPS), i....
Ole J. Mengshoel, Mark Chavira, Keith Cascio, Scot...
IFIP
2001
Springer
13 years 10 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre