In this paper we present a “lightweight” visual formalism that can be used to examine the state space complexity of an interface. The method can form a basis for designing, te...
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and stru...
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Ya...
We present a rigorous but transparent semantics definition of SystemVerilog that covers processes with blocking and non-blocking statements as well as their interaction with the s...
Martin Zambaldi, Wolfgang Ecker, T. Kruse, W. M&uu...
Ontologies, often defined as an explicit specification of conceptualization, are necessary for knowledge representation and knowledge exchange. Usually this means that ontology des...