531 search results - page 11 / 107 » Formal Methods for Networks on Chips |
96
Voted
ISPD
2004
ACM
15 years 6 months ago
2004
ACM
This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the pow...
124
Voted
VLSID
2009
IEEE
16 years 1 months ago
2009
IEEE
In this paper, we present a dynamic power management technique for optimizing the use of virtual channels in network on chips. The technique which is called dynamic virtual channe...
74
Voted
ENTCS
2008
15 years 23 days ago
2008
A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC). The network mu...
ISCA
2007
IEEE
15 years 7 months ago
2007
IEEE
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
ECBS
2008
IEEE
15 years 7 months ago
2008
IEEE
Network designers perform challenging tasks with so many configuration options that it is often hard or even impossible for a human to predict all potentially dangerous situation...