Sciweavers

531 search results - page 30 / 107
» Formal Methods for Networks on Chips
Sort
View
IJON
2008
88views more  IJON 2008»
14 years 9 months ago
Neural network construction and training using grammatical evolution
The term neural network evolution usually refers to network topology evolution leaving the network's parameters to be trained using conventional algorithms. In this paper we ...
Ioannis G. Tsoulos, Dimitris Gavrilis, Euripidis G...
MEMOCODE
2007
IEEE
15 years 4 months ago
Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
Cheng-Hong Li, Rebecca L. Collins, Sampada Sonalka...
KCAP
2011
ACM
14 years 17 days ago
LinkedDataLens: linked data as a network of networks
With billions of assertions and counting, the Web of Data represents the largest multi-contributor interlinked knowledge base that ever existed. We present a novel framework for a...
Yolanda Gil, Paul T. Groth
GECCO
2009
Springer
148views Optimization» more  GECCO 2009»
15 years 4 months ago
Evolutionary optimization of multistage interconnection networks performance
The paper deals with optimization of collective communications on multistage interconnection networks (MINs). In the experimental work, unidirectional MINs like Omega, Butterfly a...
Jirí Jaros
KCAP
2005
ACM
15 years 3 months ago
Collaborative knowledge capture in ontologies
This paper describes a new environment, COE, for capturing and formally representing expert knowledge for use in the Semantic Web. COE exploits the ease of use and rapid knowledge...
Patrick J. Hayes, Thomas C. Eskridge, Raul Saavedr...